1. Field
The present invention relates to a semiconductor memory having sense amplifiers amplifying a signal amount of data read from memory cells.
2. Description of the Related Art
Generally, in a semiconductor memory, to read data, a signal amount of the data outputted from a memory cell to a bit line is amplified by a sense amplifier. For example, a memory cell of a DRAM stores logic of data as an electric charge in a cell capacitor. The electric charge stored in the memory cell gradually decreases and in due time the data held in the memory cell is lost. Therefore, the DRAM requires periodic refresh operations in order to retain data in the memory cell.
A characteristic of retaining the electric charge of a memory cell varies depending on the position of the memory cell, manufacturing conditions, and so on. A memory cell with a poor characteristic, that, is a memory cell with a small operation margin needs to be replaced by a redundancy memory cell. A method of capable of evaluating the operation margin of a memory cell is, for example, to shorten a time interval after data is outputted from the memory cell to a bit line in response to the activation of a word line until a sense amplifier starts an amplifying operation. If the timing for the sense amplifier to start the amplifying operation is made earlier, a read failure more easily occurs in a memory cell with a smaller operation margin.
There has been proposed another method to detect a memory cell with a small operation margin, by shortening a time interval after the amplifying operation of the sense amplifier is started until a column switch is turned on (for example, Japanese Unexamined Patent Application Publication No. Hei 11-317098). There has also been proposed a method to detect a memory cell with a small operation margin, in particular, a memory cell having a minute leakage path, by increasing a time interval after a word line is activated until a sense amplifier starts an amplifying operation (for example, Japanese Unexamined Patent Application Publication No. 2001-195900).
However, in the conventional methods of evaluating an operation margin of a memory cell, signal delay depending on the position of the memory cell is not taken into consideration. For example, in a memory cell, ON timing of a transfer transistor connected to a word line is more delayed as it is more apart from a word driver. Therefore, in a case where, for example, the same amplification start timing is set for sense amplifiers corresponding to all the memory cells, the operation margins of the memory cells cannot be correctly evaluated. As a result, there is a risk of shipping semiconductor memories to be excluded as bad chips to the market.